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Similarly, for slow signals received from the peripheral bus , the bridge logic can determine from the fast clock signal input over path , and the data input over path , when to sample the signals on the peripheral bus and subsequently drive them on to the system bus Since, in preferred embodiments, the peripheral bus operates at the same clock speed as the system bus , then the peripheral bus can be arranged to support direct memory access DMA , since no data buffering is needed in the bridge logic System and method to maximize channel utilization in a multi-channel wireless communiction network. Typically, the clock speeds required by the peripheral units will be integer divisions of the clock speed chosen for the second peripheral bus. In preferred embodiments, this clock signal has a clock speed of approximately 30 MegaHertz, this being the clock speed of the system bus , and the peripheral bus System and method to maximize channel utilization in a multi-channel wireless communication network. Hence, as more and more peripheral units are connected to the bus, the overall power savings resulting from the use of the peripheral bus are reduced. For example, by reducing power consumption, it is also possible to reduce heat generation, and hence reduce the need for heat dissipating elements such as fans and heat sinks to be provided, thereby reducing cost and size. However, for the peripheral devices that are provided off-chip, there will typically be provided some corresponding on-chip logic that is connected to the peripheral bus, and is used to interface with the peripheral device.

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